创造产品，也探索底层技术。Building products. Exploring the technology beneath.
何雪熙 / Xuexi He
Redding AI 联合创始人Co-founder of Redding AI
我是何雪熙，Redding AI 联合创始人。本科就读于中国科学技术大学，随后在物理学院开展电子科学与技术方向的硕士研究。I’m Xuexi He, co-founder of Redding AI. I studied at the University of Science and Technology of China and went on to pursue master’s research in Electronic Science and Technology.
我的项目横跨 AI 应用、集成电路与机器人：从 Peture 的全栈开发，到极低温量子比特读出电路，再到仿生机器人的电控系统。My projects span AI applications, integrated circuits, and robotics—from full-stack development for Peture to cryogenic qubit readout circuits and robotic control systems.
精选项目Selected projects
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Peture · 智宠合生Peture · AI pet care
负责全栈开发与架构优化：整合 AI 对话与宠物档案，重构本地与云端数据同步，并优化 Flutter 前端缓存。Full-stack development and architecture: integrated AI conversations with pet profiles, rebuilt local–cloud synchronization, and optimized Flutter caching.
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生物仿生机器人头部Biomimetic robotic head
搭建树莓派主从控制架构，设计电机控制板，完成 16 路驱动联调，并通过插值实现面部动作的平滑过渡。Built a Raspberry Pi control system and custom motor-control PCB, integrated 16 actuator channels, and smoothed facial motion through interpolation.
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极低温量子比特读出电路Cryogenic qubit readout
设计工作于 4 K 的微弱电流读出前端及四通道阵列，完成电路设计、版图与后仿真，项目已流片。Designed a 4 K low-current readout front end and four-channel array, completing circuit design, layout, and post-layout simulation through tape-out.
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NanoDet FPGA 加速器NanoDet FPGA accelerator
基于 Im2col 与通用矩阵乘架构，实现面向实时目标检测的卷积硬件加速模块与 RTL 设计。Implemented convolution acceleration and RTL for real-time object detection using an Im2col and general matrix multiplication architecture.
工作与研究Work & research
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Redding AI · 联合创始人Redding AI · Co-founder
参与 AI 产品的探索与构建。Exploring and building AI products.
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芯耀辉科技 · 系统架构部IC design · System architecture
设计高速相位插值器，参与 SerDes 系统建模与时钟恢复行为级仿真。Designed high-speed phase interpolators and contributed to SerDes system modeling and behavioral simulation of clock recovery.
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中国科学技术大学 · 硅基半导体量子计算研究室USTC · Silicon semiconductor quantum computing laboratory
参与低温电路测试单元版图设计，并基于 FPGA 搭建 DAC 测试波形发生器。Contributed to cryogenic test-circuit layout and an FPGA-based waveform generator for DAC testing.
教育经历Education
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中国科学技术大学 · 硕士研究University of Science and Technology of China · Master’s studies
物理学院 · 电子科学与技术；简历所列预计毕业时间为 2026 年 6 月。School of Physical Sciences · Electronic Science and Technology; expected graduation listed in résumé: June 2026.
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中国科学技术大学 · 本科University of Science and Technology of China · Undergraduate studies
物理学院 · 微电子与固体电子学School of Physical Sciences · Microelectronics and Solid-State Electronics
论文Publications
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Xuexi He, Chao Luo (2026). An Energy-Efficient Charge-Sampling Readout Front-End with Floating-Inverter Amplifier. In 2026 5th International Conference on Electronics, Integrated Circuits and Communication Technology (EICCT), pp. 94–99. IEEE ↗
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Changchun Zhou, Xuexi He, Bolun Zeng, Jun Xu, Chao Luo, Guoping Guo (2025). A 200-MS/s 12-b Cryo-CMOS CS DAC for Quantum Computing. In IEEE Transactions on Circuits and Systems II: Express Briefs, 72(1), 98–102. IEEE ↗
部分荣誉Selected honors
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WaytoAGI 全球黑客松 · 合肥站WaytoAGI Global Hackathon · Hefei
徽客松 S2 特等奖、一等奖；S1 三等奖。S2: Grand Prize and First Prize. S1: Third Prize.
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中国科学技术大学「雏鹰基金」USTC “Young Eagle Fund”
「智宠合生 Peture」产品类项目获原创课题立项。Peture selected for original-project funding in the product category.